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NPU Explorer

LeNet-5 CNN推理NPU的微架构:点模块看说明,按 ▶︎ 回放一帧MNIST推理。时间轴按400MHz下RTL仿真实测的时间画。
conv1
fc1
fc2
343.1 µs
844.6 µs
177.4 µs
ready · t = 0.0 µsMACs 0 / 651,720frame latency 1,424.5 µs · FC = 72.8% of time, 9.0% of MACs

按 ▶︎ 从第一个像素开始回放;⏭︎ 跳到下一层,也可以直接拖时间轴。

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npu_chip_top · pad ringnpu_topapb_cfgdata_cacheL1 cachefmap RAM ×4cnn_calnpu_macnpu_fcSPIAPB0APB1APB1 · SRAM readbackweight bytesAXI writeAXI readir_valid & npu_enrgb FP16weightslayer outfmap rdfc3 outnpu_doneresult → APB1src_done16 internal signalsdb_outHostSPI masterIR source32×32 RGBspi2apbSPI → APB0 / APB1apb_ram_ctrlSPI readback · ROaxi_ram_ctrlAXI slave → SRAMsram_read_muxsel = spi_read_sram_enWeight SRAM2 × 2048 × 256 bitAPB0 regsPLL · gate · padAPB1 regsctrl · scale/zp · biasdata_cache_wr32 B → AXI writeasync FIFO25 bit × 8weight fetchaxi_readerweight buf1536 × 256 bitdequant ×32INT8 → FP16outmuxconv latch · FC FIFOpool114×14×6pool25×5×16fc1120fc284RGB RAM1024 × 24 bitdequant ×38 bit → FP16max_resultargmax · 4 bitmult ×96FP16add treeacc · 7 cycReLUmax pool2×2mult ×1FP16adderacc · 7 cyc+ biasReLUfc3 bypasslayer ctrl*_end chain → work_modeclk / rst genPLL · mux · ICG · ÷4 · syncdebug_mux 16:1sel = db_sel[3:0]

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