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LeNet-5 CNN推理NPU的微架构:点模块看说明,按 ▶︎ 回放一帧MNIST推理。时间轴按400MHz下RTL仿真实测的时间画。
0.5×
1×
2×
4×
By time
By MACs
conv1
fc1
fc2
343.1 µs
844.6 µs
177.4 µs
ready
· t = 0.0 µs
MACs 0 / 651,720
frame latency 1,424.5 µs · FC = 72.8% of time, 9.0% of MACs
按 ▶︎ 从第一个像素开始回放;⏭︎ 跳到下一层,也可以直接拖时间轴。
← 左右滑动看全图 →
npu_chip_top · pad ring
npu_top
apb_cfg
data_cache
L1 cache
fmap RAM ×4
cnn_cal
npu_mac
npu_fc
SPI
APB0
APB1
APB1 · SRAM readback
weight bytes
AXI write
AXI read
ir_valid & npu_en
rgb FP16
weights
layer out
fmap rd
fc3 out
npu_done
result → APB1
src_done
16 internal signals
db_out
Host
SPI master
IR source
32×32 RGB
spi2apb
SPI → APB0 / APB1
apb_ram_ctrl
SPI readback · RO
axi_ram_ctrl
AXI slave → SRAM
sram_read_mux
sel = spi_read_sram_en
Weight SRAM
2 × 2048 × 256 bit
APB0 regs
PLL · gate · pad
APB1 regs
ctrl · scale/zp · bias
data_cache_wr
32 B → AXI write
async FIFO
25 bit × 8
weight fetch
axi_reader
weight buf
1536 × 256 bit
dequant ×32
INT8 → FP16
outmux
conv latch · FC FIFO
pool1
14×14×6
pool2
5×5×16
fc1
120
fc2
84
RGB RAM
1024 × 24 bit
dequant ×3
8 bit → FP16
max_result
argmax · 4 bit
mult ×96
FP16
add tree
acc · 7 cyc
ReLU
max pool
2×2
mult ×1
FP16
adder
acc · 7 cyc
+ bias
ReLU
fc3 bypass
layer ctrl
*_end chain → work_mode
clk / rst gen
PLL · mux · ICG · ÷4 · sync
debug_mux 16:1
sel = db_sel[3:0]
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