2025.02 – 2025.08 Shanghai, China
Enrigin Technology Co., Ltd.
Digital IC Intern
Verified an AXI address-remapping IP in UVM, from test plan to 100% code and functional coverage.
Featured projects
Engineering the
Future of Silicon.
M.Eng ECE at UIUC, designing and verifying digital ICs.
Turning ideas into silicon that works,
from processor cores to AI accelerators.
Specialized in RTL Design · Design Verification · Computer Architecture
Career
Education
2024.08 – 2026.12
University of Illinois Urbana-Champaign
M.Eng in Electrical & Computer Engineering
Coursework in computer organization and design, digital systems (FPGA), VLSI system design, and digital IC design.
Featured projects
-
LeNet-5 CNN NPU 功能验证 NPU SPI VIP UVM RAL FP16 model CDC -
多周期 RV32I 处理器的 constrained-random 验证 CRV Covergroup Directed tests 4 类 bug -
五级流水线 RV32I 处理器 Pipeline RV32I Forwarding Hazards Spike / RVFI -
乱序 RV32IM 处理器 Out-of-Order RV32IM ROB Tomasulo 团队项目 -
RV32I 处理器：全定制 datapath 与物理实现 Full-Custom Virtuoso Innovus FreePDK45 - 基于 gem5 的性能建模与设计空间探索 Modeling gem5 X86 O3 SPEC CPU2006 L1D sweep
Skills
RTL Design
- Verilog
- SystemVerilog
- RTL design / synthesis
- Low-power design
- Clock / power gating
- Design Compiler
- SpyGlass (Lint / CDC)
- PrimeTime
Design Verification
- UVM
- SVA
- Constrained-random
- Functional coverage
- SystemVerilog
- VCS NLP
- Verdi
Physical Design
- Full-custom layout
- Liberty / LEF views
- Virtuoso
- Innovus
- Calibre (DRC / LVS)
Architecture & Protocols
- Computer architecture
- RISC-V
- AMBA AXI4 / APB
- SPI
- IEEE-754 FP16
Scripting & Build
- Python
- C
- Shell
- Makefile
- Bazel
- Language
- Tool
- Method
- Protocol / ISA
Research & Thoughts
The Blog
- 从评测到agent：NVIDIA用大模型做RTL设计与验证的14篇论文 AI Generated 2026.10.26
- 【计组】超标量与乱序执行（下）-ROB、提交与分支恢复 Rewritten 2026.10.17
- 【计组】超标量与乱序执行（上）-超标量、寄存器重命名与Reservation Station Rewritten 2026.10.16
- 【计组】Cache性能优化 AI Assisted 2026.10.15
- 芯片设计与验证岗位需要什么AI能力：从Anthropic的两份JD说起 AI Generated 2026.10.14
- 中国芯片行业 2027—2030 年发展趋势：需求、供给与中美产业比较 AI Generated 2026.10.12
- 低功耗设计 AI Assisted 2026.10.11
- Verilog 语法速览 Rewritten 2026.10.10
- 时钟电路 Rewritten 2026.09.16
- SystemVerilog 学习笔记 2026.08.06
Experiments & Tools
The Labs
- SV 代码解释插件 Verification
- Testbench 检错评估 Verification
- 架构图绘图套件 Diagrams
- 电脑使用时间看板 Productivity
- Mac 启动台 Productivity