About
Hi, I'm Pinxu — currently wrapping up an M.Eng in ECE at UIUC (Dec 2026) and spending most days deep in UVM testbenches, RISC-V microarchitecture, and the RTL-to-GDSII flow. Right now I'm owning pre-silicon verification on a 22 nm CNN inference NPU heading to tape-out, which has been equal parts terrifying and the best learning of my degree.
Outside of work, I'm usually outdoors — hiking trails around Illinois, planning the next road trip across a US national park, or chasing decent coffee in whatever city I land in. I also recently adopted Raspberry, a Domestic Shorthair kitten who now supervises most of my late-night debugging. I keep notes on what I'm learning here so future-me can find them again.
Looking for US new-grad roles in Digital IC Verification or RTL Design. If you're hiring or just want to talk silicon, feel free to reach out.
Education
| School | Degree | Field | Dates |
|---|---|---|---|
| University of Illinois Urbana-Champaign (UIUC) | M.Eng | Electrical & Computer Engineering | Aug 2024 – Dec 2026 |
| University of Electronic Science and Technology of China (UESTC) | B.S. | Microelectronics Science and Engineering | Aug 2019 – May 2023 |
Skills
- HDL & Modeling
- SystemVerilog (RTL & TB) Verilog C-Model Gem5
- Verification
- UVM Coverage-driven VIP Configuration RVFI
- EDA Tools & Flows
- Synopsys VCS / Verdi Design Compiler Spyglass (Lint/CDC) PrimeTime Calibre (DRC/LVS)
- Infrastructure & Tools
- Git JIRA Jenkins Bazel Makefile Claude Code CLI Cursor
Contact
- pinxuw@gmail.com
- Phone
- +1 (217) 417 0921
- Address
- Champaign IL, US
- GitHub
- github.com/CoffeeBeforeArch7
Privacy
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