About
Pinxu Wang — Digital IC verification & RTL engineer focused on UVM, RISC-V microarchitecture, and full RTL-to-GDSII flow. Currently completing an M.Eng at UIUC (Dec 2026) and contributing pre-silicon verification on a 22 nm CNN inference NPU tape-out. Target roles: US new-grad Digital IC Verification or RTL Design.
Education
| School | Degree | Field | Dates |
|---|---|---|---|
| University of Illinois Urbana-Champaign (UIUC) | M.Eng | Electrical & Computer Engineering | Aug 2024 – Dec 2026 |
| University of Electronic Science and Technology of China (UESTC) | B.S. | Microelectronics Science and Engineering | Aug 2019 – May 2023 |
Skills
- HDL & Modeling
- SystemVerilog (RTL & TB) Verilog C-Model Gem5
- Verification
- UVM Coverage-driven VIP Configuration RVFI
- EDA Tools & Flows
- Synopsys VCS / Verdi Design Compiler Spyglass (Lint/CDC) PrimeTime Calibre (DRC/LVS)
- Infrastructure & Tools
- Git JIRA Jenkins Bazel Makefile Claude Code CLI Cursor
Contact
- pinxuw@gmail.com
- Phone
- +1 (217) 417 0921
- Address
- Champaign IL, US
- GitHub
- github.com/CoffeeBeforeArch7