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Uses

Tools, EDA flows, and dotfiles that show up in my day-to-day digital IC verification and RTL work. Versions reflect what I actually run today.

HDL

Hardware description and modeling languages I write day-to-day.

  • SystemVerilog (IEEE 1800-2017) — RTL design and testbench authoring
  • Verilog-2001 — Legacy module integration and library cells
  • C / C++17 — Reference C-models and cycle-accurate simulators
  • Python 3.12 — Test plan automation, log post-processing, coverage analysis

Verification

Methodology and IP I lean on for pre-silicon verification.

  • UVM 1.2 — Constrained-random + coverage-driven testbenches
  • Synopsys AXI VIP — AMBA AXI4 / AXI4-Lite stimulus and protocol checking
  • RVFI — RISC-V formal interface for instruction-trace checking
  • SVA — Concurrent assertions for protocol and interface checks
  • Functional Coverage — Covergroups, cross-coverage, exclusion files for signoff

EDA Tools

Vendor toolchain — versions reflect the lab/internship environments I have used.

  • Synopsys VCS 2024.03 — Simulation, +UVM_TESTNAME / plusargs driven flows
  • Synopsys Verdi 2024.03 — Waveform + interactive debug, KDB databases
  • Synopsys Design Compiler 2023.12 — RTL synthesis to Nangate / educational stdcell libraries
  • Synopsys PrimeTime 2023.12 — Static timing analysis, SDF back-annotation
  • Synopsys Spyglass 2023.06 — Lint and CDC checking
  • Siemens Calibre 2023.4 — DRC / LVS for the RV32I tape-out flow
  • Cadence Innovus 22.1 — Place and route, RV32I GDSII closure

Editor / IDE

Where the code actually gets written.

  • Neovim 0.10 — Daily driver; clangd + verible-verilog-ls + Treesitter
  • VS Code 1.94 — SystemVerilog (mshr-h.veriloghdl), GitLens, remote SSH to lab boxes
  • Cursor 0.42 — AI-assisted refactors on larger DV scripts
  • Obsidian 1.7 — Project notes, study plan, daily logs — source of truth for /notes content
  • iTerm2 + zsh — Terminal multiplexing via tmux 3.4

Infra

Tools wrapped around the code — from CI to this site.

  • Git 2.46 — Worktrees for parallel branches on long simulation runs
  • GitHub Actions — Lint + typecheck + build gate on every push
  • JIRA — Bug tracking and verification signoff at Enrigin
  • Jenkins — Nightly regression dispatch over LSF grids
  • Bazel 7 — Hermetic C-model builds, reusable across regressions
  • GNU Make 4.4 — Per-block compile and run flow scaffolding
  • Claude Code CLI — Agent-driven test plan drafts and code review
  • Astro 5 + Cloudflare Pages — This site — Workers + D1 backing visit log and comments