AXI Address Mapping & Hash Routing UVM Verification

Overview

Pre-silicon verification of the AXI Address Mapping, Hash Routing, and Burst Clipping blocks for a NUMA-based SoC fabric. I built a parameterized UVM environment integrated with Synopsys AXI VIPs, owned the ID Remap/Reorder verification flow, and closed 100% code + functional coverage to meet tape-out signoff.

Tech Stack

SystemVerilog · UVM · Synopsys AXI VIP · VCS / Verdi · coverage-driven verification · bit-accurate reference models

Highlights

• Test plans for Address Mapping, Hashing, and Burst Clipping; drove spec revisions through design reviews and resolved several SoC spec gaps.
• Parameterized UVM env with a macro + plusarg layering — macros control structural parameters (port count, ID width), plusargs control test-case + verbosity. Enabled cross-IP reuse and multi-instance adaptation without rebuilds.
• ID Remap/Reorder verification after the AXI ID width was extended 9-bit → 12-bit. Designed sequences covering all-identical, all-unique, and random-outstanding ID scenarios; root-caused a CAM aliasing corner case that only triggered at specific ID/address combinations.
• Bit-accurate scoreboard for NUMA hash routing and 512B / BL1 boundary clipping. Covered AxSize 0–7, unaligned addresses, narrow transfers, and sub-burst reordering.
• Coverage closure: worked with the RTL team on coverage collection and waiver analysis; reached 100% code + functional coverage prior to tape-out.

Key Decisions

• Bit-accurate reference model over behavioral. Hashing and clipping bugs manifest as wrong sub-burst values, not just wrong totals. Bit-level diff is what lets you point at the exact byte that broke. Cost was higher dev time, paid back in debug speed.
• Three ID-distribution sequences (identical / unique / random) instead of pure-random. Random alone doesn’t reliably trigger boundary cases. Layering the three lets the env hit ordered-baseline, full-reorder, and realistic-traffic regimes in one regression.
• Backward-compatible ID extension. When the spec moved 9 → 12 bit I kept 9-bit behavior as a strict subset via zero-pad, avoiding retiring the existing testcase library mid-project.