AXI Address Mapping & Hash Routing UVM Verification

实习项目 — Enrigin Technology(Shanghai)。美国岗最强弹药:工业级 UVM 经验。

← 项目索引

一句话总结

基于 UVM 的参数化验证环境,集成 AXI VIPs,完成 Address Mapping / Hashing / Burst Clipping 等模块的功能验证,推动 spec 修订,达成 100% code + functional coverage,满足 tape-out 标准。

简历描述(原文)

Digital IC Verification Engineer Intern | Enrigin Technology AXI Address Mapping & Hash Routing Module Verification

Extracted SoC/Micro-Arch feature lists and developed comprehensive test plans for Address Mapping, Hashing, and Burst Clipping; drove Spec revisions and successfully passed design reviews.

Architected a parameterized UVM verification environment integrated with AXI VIPs, utilizing macros and plusarg to enable seamless cross-IP portability and multi-instance adaptation.

Led incremental verification for ID Remap/Reorder modules: extended AXI ID width from 9-bit to 12-bit and designed reorder sequences covering all-identical, all-unique, and random ID outstanding scenarios; identified and resolved a critical CAM addressing corner case.

Developed bit-accurate Reference Models in Scoreboard for NUMA-based Hashing and 512B/BL1 Boundary Clipping, ensuring 100% functional coverage across varied AxSize 0–7, unaligned addresses, and narrow transfers.

Collaborated with the RTL team on coverage collection and waiver analysis, achieving 100% code and functional coverage to meet project tape-out standards.

关键亮点

✅ 工业级 UVM + AXI VIP 实战(美国 verification 岗硬通货)
✅ AXI 协议深度(AxSize、unaligned、narrow transfer、burst boundary)
✅ Reference Model bit-accurate(NUMA Hashing、512B/BL1 Clipping)
✅ 真实 silicon impact:发现 CAM addressing corner case
✅ 覆盖率达标:100% code + functional,满足 tape-out

面试优先级

⭐⭐⭐⭐⭐ — DV / SoC / 总线岗位首推。CPU 岗位作为补充展示,体现工程严谨度。

进度

技术细节填完(UVM 架构、AXI 协议要点)
Reference Model 数学表达式整理(NUMA hashing 公式)
30 个深挖问答
CAM corner case 完整故事(发现→定位→修复)
关键决策 / trade-off
英文版 STAR 三档
架构图默画(verification env 框图)

入口

01_技术细节
02_深挖问答
03_关键决策
04_数据指标
05_英文版讲解

Key Decisions

面试时问 “你为什么这么做” 是常见题。提前整理决策 + 备选方案 + 你为什么选这个。

决策 1:UVM env 的参数化方式 - macro + plusarg

选了什么

\definemacro(build-time)++plusarg`(run-time)双层参数化。

替代方案

纯 macro:不灵活,改一次要重编
纯 plusarg:build 慢(所有 variant 都得编)
用 uvm_config_db 全跑动:动态性最强,但代码冗长

选这个原因

macro 控制结构性参数(端口数、ID 宽度) — build 期决定,代码生成最优
plusarg 控制 testcase / verbosity — 不改 build,跑不同 case 快
双层组合让 cross-IP 切换最高效

Trade-off

✅ 灵活 + 高效
⚠️ 学习曲线高,新人接手要解释清楚

决策 2:Reference Model bit-accurate 还是 behavioral?

选了什么

Bit-accurate(NUMA Hashing 和 Boundary Clipping)。

替代方案

Behavioral:只判结果对错,不要求中间值
Cycle-accurate:连时序也要对(过度复杂)

选这个原因

Hashing 出错会导致路由错误,bit-accurate 才能精确定位
Boundary Clipping 涉及拆分,sub-burst 顺序 / 个数错都是 bug,bit-level 比对必要

Trade-off

✅ 调试时能精确定位 RTL bug
⚠️ 开发成本高,需要深入理解 RTL 实现

决策 3:ID outstanding 三种 sequence 设计

选了什么

All-identical / All-unique / Random 三档。

替代方案

只 Random:覆盖广但边界 case 不一定 trigger
只边界 case:难压出 corner case 组合

选这个原因

All-identical → 强制按序,验证基础顺序逻辑
All-unique → 完全乱序,验证 reorder 极限
Random → 现实分布,压出意外组合

Trade-off

✅ 三档覆盖典型 + 边界 + 现实场景
⚠️ 需要写 3 套 sequence,工作量较大

决策 4:9-bit → 12-bit ID 扩展的 backward compatibility

选了什么

保留 9-bit 兼容(ID < 512 时行为一致)。

替代方案

完全切换 12-bit,旧 testcase 全废
保留两套 env(9-bit / 12-bit)

选这个原因

项目持续推进,旧 testcase 不能废
12-bit 是超集,9-bit 自动是子集

Trade-off

✅ 兼容性好
⚠️ Reference Model 处理 ID 时多一层 zero-pad 逻辑

决策 5:Coverage waiver 的尺度

选了什么

(待填,基于实际项目)

一般原则

spec 明确允许的 → 可 waive
实际不可达的逻辑路径 → 可 waive
“测不到但可能有 bug” → 不能 waive,要写 directed test

TODO

补充实际项目的具体决策点
标注每个决策对应的 NDA 边界

Metrics

面试讲项目要带数字。模糊词(“挺好的”、“挺快的”)扣分,精确数字加分。

关键 metric(简历声明)

指标	数值	说明
功能覆盖率	100%	tape-out 标准
代码覆盖率	100%	line / toggle / FSM / branch / cond
AXI ID 宽度扩展	9-bit → 12-bit	增量验证
AxSize 覆盖	0–7	1B 到 128B
关键 corner case	CAM addressing	找到并修复

待补充的细节数据

这部分需要你填,带数字最有说服力。

Verification env 规模

代码行数:多少?
Sequence / testcase 数量:多少?
Reference Model 行数:多少?
跑完一轮 regression 时长:多少?

覆盖率收敛过程

自动 random test 跑到多少 % ?
后续加 directed test 多少个填到 100% ?
waiver 多少条?

Bug discovery

你发现的 bug 总数:多少?
其中 critical 级别:多少?(CAM corner case 是其一)
平均 debug 时长:多少?

工时

项目持续多久?(weeks / months)
你 onboard 多久能独立提 testcase?
跟 RTL team 协作频率?

跟 baseline 对比(如果有)

之前 9-bit ID 时覆盖率多少?扩到 12-bit 后用了多久达 100%?
接手前 env 多大,你扩展后多大?

量化讲法模板

✅ “AXI ID 从 9-bit 扩展到 12-bit,设计 X 个新 sequence,新增 Y 个 cover bin,2 周内功能覆盖率达 100%”

✅ “Reference Model bit-accurate 实现 NUMA hashing,精确比对到 N bit,发现 RTL CAM addressing 在特定 ID/地址组合下的 corner case bug”

❌ “覆盖率挺高的,bug 也找了不少”(模糊)

TODO

在 NDA 允许范围内填具体数字
凡是有数字的地方,都准备 follow-up:这个数字怎么测的?对比什么?

STAR Narratives (English)

美国岗必练。中文流畅 ≠ 英文流畅。录音回放,直到无填充词、语速稳定。

关键术语对照

中文	English
验证	Verification
覆盖率	Coverage(functional / code)
测试用例	Testcase / Sequence
参考模型	Reference Model / Predictor
计分板	Scoreboard
监控器	Monitor
序列	Sequence
寄存器	Register
地址映射	Address Mapping
哈希路由	Hash Routing
突发传输	Burst Transaction
边界裁剪	Boundary Clipping
乱序完成	Out-of-order Completion
在途事务	Outstanding Transaction
内容可寻址存储器	CAM (Content-Addressable Memory)
边界情况(corner)	Corner Case
流片	Tape-out
协议遵从	Protocol Compliance

30-Second Elevator Pitch

适合自我介绍带过 / 电话 OA。

During my internship at Enrigin Technology, I worked as a Digital IC Verification Engineer
on AXI bus subsystem verification. I built a parameterized UVM environment integrated with
AXI VIPs, and I was responsible for verifying the address mapping, hash routing, and burst
clipping modules. I developed bit-accurate reference models for NUMA-based hashing and
boundary clipping, and we achieved 100% functional and code coverage to meet tape-out
standards. The most exciting part was identifying a critical CAM addressing corner case
that the random tests missed.

(~60 秒,可压到 30 秒,删掉 NUMA 细节即可)

2-Minute Standard Version(STAR)

Situation

At Enrigin Technology, I was an intern on the SoC verification team working on a NUMA-based
multi-channel memory subsystem. The block I owned was responsible for address mapping —
deciding which memory channel each transaction should route to — plus burst clipping at
512-byte and BL1 boundaries.

Task

My task was to architect the UVM verification environment, develop testplans for the address
mapping, hashing, and burst clipping modules, and drive coverage closure to tape-out quality.
I also led the incremental verification when the AXI ID width was extended from 9 to 12 bits.

Action

I architected a parameterized UVM environment using `define macros for build-time
configuration and plusargs for runtime control, which made the env reusable across
different IP instances. For the reference models, I implemented bit-accurate predictors
for NUMA hashing and boundary clipping — making sure the comparison was precise enough
to catch any RTL deviation. For the ID extension, I designed three sequence patterns:
all-identical IDs to validate ordered behavior, all-unique IDs to stress reorder logic,
and random IDs for realistic mix.

Result

We achieved 100% functional and code coverage, satisfying tape-out criteria. The most
impactful finding was a critical CAM addressing corner case — the bug only triggered
under a specific combination of ID values and address ranges. After tracing the waveform
and collaborating with the RTL designer, we identified the root cause in the CAM lookup
logic and fixed it before tape-out.

15-30 Minute Deep-Dive Version

现场 deep dive 时讲。要能即兴白板画 verification env 框图、AXI burst clipping 时序图、CAM corner case 波形。

大纲

项目背景(2 min):SoC 架构、为什么需要 hash routing
AXI 协议关键点(3 min):channel / outstanding / boundary
UVM env 架构(5 min):agent / scoreboard / RM,白板画框图
NUMA Hashing RM 实现(3 min):hash function 数学
ID Reorder 三种 sequence(2 min)
CAM Corner Case Story(8-10 min):full STAR 故事 + 波形
Coverage Closure(2 min):metric + waiver philosophy
Reflection(2 min):学到了什么 / 如果重做会怎么改

高频英文 Q&A 应答

Q: Walk me through how a read transaction flows through your verification env.

A: (待填,描述 master VIP 发 AR → DUT hash → reference model 算 expected → monitor 抓 R → scoreboard 比对)

Q: How did you find the CAM corner case if the random sequence didn’t initially catch it?

A: (待填,讲 coverage hole → directed test → 或 stress test 偶发 trigger)

Q: What’s the trade-off between bit-accurate and behavioral reference models?

A: (待填)

录音 / 模拟练习清单

30-second pitch 录 ≥ 5 次,无填充词
2-minute STAR 录 ≥ 5 次,语速稳定
CAM corner case 故事录 1 次完整版
Mock interview 用英文做 1 次,自评/友评