RV32I CPU Datapath — RTL to GDSII (FreePDK 45 nm)

Overview

End-to-end RTL → GDSII implementation of an RV32I five-stage pipelined datapath on the FreePDK 45 nm node. Custom-laid the 32 × 32 register file in Cadence Virtuoso, then ran the synthesized core through DC, Innovus, and PrimeTime to a clean DRC/LVS signoff at 500 MHz.

Tech Stack

SystemVerilog · Cadence Virtuoso · Synopsys DC · Cadence Innovus · Synopsys PrimeTime · Mentor Calibre (DRC/LVS) · Tcl · SDC · multi-corner STA

What I Built

• Full-custom 32 × 32 register file in Cadence Virtuoso with TG-based latch storage cells. Hand-routed M1–M3, DRC/LVS clean. Sized for the access patterns of a single-issue 5-stage pipeline (two reads + one write per cycle).
• RV32I 5-stage pipelined datapath in SystemVerilog. Resolved X-propagation issues with VCS -xprop and SVA assertions. Replaced tri-state read buses with one-hot MUXes — easier STA, no contention, no driver-fight verification headaches.
• Synthesis → P&R → STA flow with parameterized Tcl scripts. SDC constraints cover clock, async reset synchronizer, and IO timing. STA runs over a 4-corner matrix (TT / SS / FF / SF) at the signoff stage.

Results

• DRC + LVS clean at the final GDSII milestone.
• 500 MHz timing closure with WNS +5 ps post-route (signoff corner).
• ~8,500 μm² core area (synthesis + placed).
• All hierarchical paths covered in the multi-corner STA report — no negative slack on any path/corner.

Key Decisions

• One-hot MUX instead of tri-state read bus. Tri-state requires enable-disjoint verification and is harder for modern STA tools to reason about. A one-hot MUX has the same fan-in, no contention class, and a clean timing graph.
• Full-custom RegFile in Virtuoso rather than the standard-cell flow. The synthesized variant met timing but used roughly 3× the area on one of the densest blocks in the datapath. Hand-laying yields a denser block and exposes the layout-vs-synthesis tradeoffs directly.
• X-propagation cleanup via VCS -xprop + SVA, not just defensive resets. -xprop surfaces ambiguity at the source, and SVA assert property(!$isunknown(...)) lets regression verify the cleanup automatically.