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Projects

Four digital-IC projects spanning verification, RTL design, physical design, and AI accelerators.

RV32I CPU Datapath — RTL to GDSII (FreePDK 45 nm)

DRC/LVS clean, 500 MHz timing closure

Feb 2025 – Apr 2025 · Course project, UIUC VLSI

Full RTL → GDSII flow on FreePDK 45 nm — DRC/LVS clean, 500 MHz timing closure.

  • RTL
  • Physical Design
  • STA
  • Virtuoso
  • RISC-V