Projects
Four digital-IC projects spanning verification, RTL design, physical design, and AI accelerators.
AXI Address Mapping & Hash Routing UVM Verification
tape-out signoffMay 2024 – Sep 2024 · Digital IC Verification Engineer Intern, Enrigin Technology (Shanghai)
Industrial UVM internship — parameterized AXI verification, ID Remap/Reorder, 100% coverage signoff.
- Verif
- UVM
- AXI
- SoC
NPU Chip Design & Verification — CNN Accelerator (Tape-out)
Silicon-validatedFeb 2026 – present · Team-developed; personal ownership: pre-silicon verification
22 nm CNN inference NPU, pre-silicon verification ownership through tape-out and silicon validation.
- Verif
- AI
- RTL
- NPU