Projects
Four digital-IC projects spanning verification, RTL design, physical design, and AI accelerators.
Single-Issue RISC-V Out-of-Order Pipeline Processor
verified in simulationSep 2024 – Dec 2024 · Course project, UIUC ECE Computer Architecture
Single-issue Tomasulo RV32IM with reorder buffer, branch prediction, and split L1 cache hierarchy.
- CPU
- RTL
- Tomasulo
- Cache
- RISC-V
RV32I CPU Datapath — RTL to GDSII (FreePDK 45 nm)
DRC/LVS clean, 500 MHz timing closureFeb 2025 – Apr 2025 · Course project, UIUC VLSI
Full RTL → GDSII flow on FreePDK 45 nm — DRC/LVS clean, 500 MHz timing closure.
- RTL
- Physical Design
- STA
- Virtuoso
- RISC-V
NPU Chip Design & Verification — CNN Accelerator (Tape-out)
Silicon-validatedFeb 2026 – present · Team-developed; personal ownership: pre-silicon verification
22 nm CNN inference NPU, pre-silicon verification ownership through tape-out and silicon validation.
- Verif
- AI
- RTL
- NPU