Projects
Four digital-IC projects spanning verification, RTL design, physical design, and AI accelerators.
NPU Design & Verification — CNN Inference Accelerator
UVM env built, coverage closed, CDC signed offFeb 2026 – present · Team-developed; personal ownership: functional verification
22 nm CNN inference NPU — owned the verification side: UVM environment, bit-true scoreboard, coverage closure, CDC sign-off.
- Verif
- AI
- RTL
- NPU
Single-Issue RISC-V Out-of-Order Pipeline Processor
verified in simulationSep 2024 – Dec 2024 · Course project, UIUC ECE Computer Architecture
Single-issue Tomasulo RV32IM with reorder buffer, branch prediction, and split L1 cache hierarchy.
- CPU
- RTL
- Tomasulo
- Cache
- RISC-V
RV32I CPU Datapath — RTL to GDSII (FreePDK 45 nm)
DRC/LVS clean, 500 MHz timing closureFeb 2025 – Apr 2025 · Course project, UIUC VLSI
Full RTL → GDSII flow on FreePDK 45 nm — DRC/LVS clean, 500 MHz timing closure.
- RTL
- Physical Design
- STA
- Virtuoso
- RISC-V